Object Detection for the Duckiebot

2023

Abbey Road by the Quackles

Obstacle avoidance implemented using Yolov5 for object detection and a reactive Braitenberg controller on the Duckiebot platform. This project ranked within the top 10 among 2023 final-year projects.

Python Logo ROS Python Logo Python

Final-year undergraduate project to investigate the Duckiebot platform for Machine Learning by implementing an object detection model. A pre-trained YOLOv5 model, fine-tuned with a publicly available Duckietown dataset, was utilised to detect Duckietown-specific objects in Python.

To enable autonomous object avoidance, a simple Braitenberg controller was employed. The final solution could detect objects (duckies) in the scene and compute wheel commands to avoid the objects for relatively simple scenarios. The project formed a foundational model that future students can improve and build upon for more sophisticated behaviors.​​​​​​​​​​​​​​​​

Thesis Github Duckietown Article
Hand-Held, 6.4V Pipe Bender

2023

A device designed for the final-year design course to bend 6mm steel pipes with an inner diameter of 3mm for bend angles up to 90 degrees.​​​​​​​​​​​​​​​​

Python Logo Solidworks Mathcad Logo style= Mathcad

​​​​​​​​​​​​​​​The year-long process was designed to follow the general Product Development Process of concept generation, basic design, detail design, design for prototyping, parts procurement, and testing. The product was constrained by several User Requirements (URs) regarding performance, budget, and mandatory features.

Design decisions had to be motivated by rigorous calculations based on mechanical strength, output torque, amperage, etc. that optimized or accounted for the various URs. Where calculations were unfeasible, sound engineering judgment had to be employed with a valid explanation. A 3D CAD model was generated using the various outputs of detail design.

From the detailed calculations and 3D model, the top 25% of designs were determined to be produced into prototypes, which mine was one of them. At this stage, we also formed groups of four. The next stage was to modify the design appropriately for prototyping. This meant accommodations for sheet metal bending and 3D printing.

Image Description
Finally, all the design parts were obtained from the workshop, and the model was integrated. This was an empowering moment when the product was finally in hand after being designed entirely from a sketch. In the final demonstration, the product achieved all the URs except for being able to bend the strongest 6mm Carbon Steel pipe. It was diagnosed that the plastic covers around the bending arm were generating friction when loaded, which was unaccounted for. Despite this, I was extremely proud of the product my team put together and was seeded with a passion for design.​​​​​​​​​​​​​​​​

Simplified Power Plant Specification

2023

High level power plant analysis
Image courtesy of A/Prof WF Fuls produced for the MEC41083S 2023 course.

A final-year Systems Engineering project involved designing a simplified Biomass Steam Power Plant. Groups of students worked on different subsystems, with my responsibility being the Steam Generator's basic design.​​​​​​​​​​​​​​​​

Mathcad Logo style= Mathcad

This project was designed to give students a tangible introduction to Systems Engineering. The User Requirement Specification (URS) detailed the type and performance requirements of the desired Power Plants. Additional requirements concerned environmental and business (Costing, contracting, and operation) requirements. Students were then given several documents outlining the operation of the highly simplified power plants.

Students had to follow a Systems Engineering approach of initially conducting a High-level analysis. For this purpose, students were given "typical" running value ranges which could be used to analyse the water-steam cycle as well as the air and fuel cycle using Mathcad. Finally, operating conditions were determined by optimising for efficiency. Later on in the project, cost optimisation was incorporated to determine the final operating conditions.

A particularly crucial aspect of the course was defining proper requirements for the system. High-level requirements were generated from the URS, Functional Analysis, and the High-level Analysis. Interface requirements were generated for all the interfaces between subsystems.

Another important part of the course was to introduce students to proper documentation. This included numbering, revision numbering, and a strict documentation format. Given the iterative nature of sizing a power plant in which lower-level design decisions change operating conditions, revision numbering was crucial. Being a group project, version control was necessary to ensure all students were working with the correct documentation.

Once the High-level specification was completed, students were given one of seven sub-systems to similarly generate an analysis, functional analysis, and finally a Sub-system specification. My subsystem related to the Steam Generator and required the specification of the furnace bed size, superheater heat exchanger, and various other aspects of the generator.​​​​​​​​​​​​​​​​

The course culminated with producing a "Power Plant Specification" which included Prime Item Diagrams (PID), system definition, Functional Allocation, requirements for functional, operational, reliability, availability, constraints and standards.​​​​​​​​​ ​​​​​​​​​​​​​​

VHDL model of an ADC

2022

Block diagram of ADC model
This block diagram is for illustration purposes only.

A synthesisable VHDL Model of a Analog to Digital Converter (ADC) for the purpose of on-target firmware and interface testing​​​​​​​​​​​​​​​​.

Mathcad Logo style= VHDL

Part of a vacation work assignment at a company that uses FPGAs for Digital Signal Processing. VHDL, a hardware description language, is used for designing FPGA systems by providing simulation, synthesis, and verification tools to support the design process.

The ADC model was part of a larger company project to create a synthesisable model of their entire hardware solution to enable firmware and interface testing. In this case, synthesizable means that the model would be able to be deployed on-target, i.e., on an FPGA. The key concern with the model was that the response should have the same number of I/Os and behave according to the specifications in the datasheet. ​​​​​​​​​​​​​​

What to find out more about any of the projects?
Contact Me.